Electrostatic discharge (ESD) protection circuits are routinely used to protect integrated circuits from damage caused by electrostatic discharge. However, local ESD protection is a major challenge for low-voltage integrated circuits. For example, complimentary metal oxide semiconductor (CMOS) technologies are becoming smaller and smaller, such as when implemented using 0.13 μm or 65 nm CMOS processes. These process technologies are typically associated with corresponding reductions in transistor gate oxide thickness. Gate oxides with reduced thickness are more sensitive to voltage overstress.